1. Field
The present invention generally relates to semiconductor memory devices, such as dynamic random access memory (“DRAM”) devices. More particularly, the present invention relates to system and method for refreshing a DRAM device without interrupting or inhibiting read or write operations on the DRAM device.
2. Description of Related Information
Semiconductor memory devices are used to store electronic data. One type of semiconductor memory devices is a static random access memory device or an “SRAM” device, An SRAM device typically uses several transistors within each memory cell of the device to store electronic data. FIGS. 1 and 2 illustrate examples of prior art SRAM cells including six transistors and four transistors, respectively. SRAM devices have the benefit of not requiring any refresh cycles to maintain stored data. On the other hand, SRAM memory cells typically include a larger number transistors which increases the cost and size of these semiconductor memory devices relative to other types of devices.
Another type of semiconductor memory device is a dynamic random access memory device or a “DRAM” device. A DRAM device typically includes fewer transistors than an SRAM device, and one or more capacitors within each memory cell of die device to store electronic data. Because DRAM devices use capacitors for storage, DRAM devices require periodic refreshing in order to maintain stored data. FIG. 3 illustrates a one transistor (IT) DRAM cell. The IT cell may be refreshed by reading the cell first and then writing back its data to the cell.
FIGS. 4-7 illustrate examples of four transistor (4T) DRAM cells, which also require refreshing. The 4T DRAM cells are sometimes referred as “quasi-static” cells. A 4T cell may be refreshed simply by turning on the word line for a short period of time, provided that both bitlines have been charged up to logic 1. Some merits of a 4T DRAM cell include: (i) it is smaller in size compared to 6T static cell, which allows higher density; (ii) it offers better access speed and cell stability than a 1T DRAM cell; and (iii) it is simple to refresh.
The present invention provides a system and method for refreshing a DRAM device, such as a device including 4T DRAM cells, in a manner that does not interrupt or inhibit read and write operations.